Certain processor architectures, such as the ARM® architecture, employ a security extension that characterizes some transactions by a security status, being either “secure” or “non-secure.” This characterization allows a processor and associated devices to distinguish between different transactions, as well as to prevent unauthorized access to protected resources and communications. In contrast, certain interconnect or bus architectures, such as Peripheral Component Interconnect Express (PCIe), do not accommodate a comparable security status within their respective transactions.